DDR Compliance Simulation in Seconds, Not Days
Summary
Host Zach Peterson interviews Ben Dannon and Tyler Huddleston from Signal Edge Solutions about high-speed PCB design challenges, including crosstalk, thick boards, and power delivery. They demonstrate MemCheck Pro, a tool that accelerates DDR compliance analysis from days to seconds by processing existing simulation data. The episode also covers IBIS model quality and previews upcoming tools for automated power integrity optimization.
Topics discussed
Introduction: Crosstalk challenges and guest introductions
Signal Edge Solutions growth and Tyler's background
Challenges with thick boards, inductance, and power delivery
Impact of board thickness on SI/PI and capacitor optimization
DDR simulation bottlenecks and the MemCheck Pro solution
Understanding simulation corners and bidirectional bus analysis
IBIS model quality issues and verification best practices
Live demo: MemCheck Pro compliance analysis and reporting
Future tools for control loop optimization and conclusion
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